Google Recruitment 2021 | FrontEnd CAD Engineer | BE/ B.Tech – Computer Science/ Electrical Engineering | Bangalore
Company: Google India Pvt Ltd
Google Recruitment 2021:- Google Inc. is an American multinational technology company specializing in Internet-related services and products. These include online advertising technologies, search, cloud computing, and software. Most of its profits are derived from AdWords, an online advertising service that places advertising near the list of search results.
Google was founded by Larry Page and Sergey Brin while they were Ph.D. students at Stanford University. Together they own about 14 percent of its shares but control 56 percent of the stockholder voting power through supervoting stock. They incorporated Google as a privately held company on September 4, 1998.
Website: www.google.com
Position: FrontEnd CAD Engineer
Experience: 2+ years
Salary: Best In Industry
Job Location: Bangalore
Education:
- Bachelor’s degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent practical experience.
- Experience in developing, supporting and debugging RTL tools and flows.
Responsibilities:
- Design, develop and deploy new RTL and/or DV flows, tools and features.
- Support (improve through profiling) execution of the tools and flows currently used in the RTL and/or DV design process.
- Design, develop, and support design methodologies, automation scripts, and write documentation.
- Be able to quickly ramp up on an existing front end methodology and support multiple projects.
Preferred Qualifications:
- Experience with developing and supporting RTL build and compilation flows, RTL connectivity flows, and IP to ASIC handoff/release flows.
- Experience in developing and supporting Design Data Management solutions (git/perforce), and continuous integration flows (Jenkins).
- Experience and understanding of multiple EDA design tools: VCS, Verdi, Spyglass, Coretools/Magillem, Cadence Xcelium.
- Exposure to front end design automation/CAD flows, including RTL lint, clock domain crossing, IP Release flow.
- Basic understanding of Verilog/System-Verilog RTL.
- Excellent scripting skills in Perl and/or Python, Makefile, Shell.
Apply Link: Job Expired
